The semiconductor industry is constantly optimizing the fabrication process for MOSFET devices. Current trends in VLSI fabrication of CMOS devices are toward reducing the number of photolithographic masking steps, while providing additional design benefits. The conventional CMOS fabrication process uses four different masking steps to perform four implantations in the NMOS/PMOS source/drain regions. One approach to process optimization is to reduce the number of masking steps, thereby minimizing process induced defects, and substantially reducing manufacturing cost.
Another approach to process optimization is to use self-aligned silicides (salicides) to improve the series resistance of the MOST. Typically, VLSI processes for fabrication of MOST, with shallow source/drain structures, require narrow sidewall spacer widths (e.g., 800 to 1,200 .ANG.) for the N+source/drain implant. The use of the narrow spacer insures the alignment of the N+ ateral edge of the source/drain regions with the poly gate edge. In contrast, the use of a wider spacer may be required in VLSI processes using salicides. For example, if titanium disilicide is used as the salicide material, a wider spacer (e.g., 2,000 .ANG.) is required to avoid bridging of the gate region to the source/drain regions during the salicide formation. Consequently, the use of salicides for the fabrication of MOS transistors with shallow source/drain structures imposes additional process constraints.